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These octal D-type flip-flops are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. The ’LVTH273 devices are positive-edge-triggered flip-flops with a direct-clear input. Information at the data (D) inputs meeting the setup-time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.
Supply Voltage (max)(V) | 3.6 | Number of Channels | 8 | Supply Current (max)(µA) | 5000 |
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IOL (max)(mA) | 64 | Supply Voltage (min)(V) | 2.7 | Clock Frequency (max)(MHz) | 150 |
Please check the type/dimensions/specifications of the part SN74LVTH273PWRG4 in the ABT Octal D-Type Flip-Flops With Clear, 3.3-V series.
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